"Subthreshold-current reduction circuits for multi-gigabit DRAM's."

Takeshi Sakata et al. (1994)

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DOI: 10.1109/4.303713

access: closed

type: Journal Article

metadata version: 2023-05-03

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Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki:
Subthreshold-current reduction circuits for multi-gigabit DRAM's. IEEE J. Solid State Circuits 29(7): 761-769 (1994)

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